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Hardware Design: Architecture and Interfacing Techniques 4-1 Introduction 4-2 Architecture 4-5 Basic Microprocessor Chip 4-5 Microprocessor Registers 4-5 Memory-to-Memory Architecture 4-9 Context Switching 4-11 T-2 9900 FAMILY SYSTEMS DESIGN TABLE OF CONTENTS Memory 4-12 Memory Organization 4-13 Memory Control Signals 4-15 Static Memory 4-23 Dynamic Memory 4-25 Buffered Memory 4-28 Memory Parity 4-28 Memory Layout 4-30 Instruction Execution 4-32 Timing 4-32 Cyclic Operation 4-35 Input/Output 4-42 Direct Memory Access 4-42 Memory Mapped I/O 4-43 Communications Register Unit (CRU) 4-45 CRU Interface 4-46 CRU Interface Logic 4-46 Expanding CRU I/O 4-47 CRU Machine Cycles 4-47 CRU Data Transfer 4-51 CRU Paper Tape Reader Interface 4-54 Burroughs SELF-SCAN Display Interface 4-57 Interrupts 4-59 Reset 4-60 Load 4-61 Basic Machine Cycle 4-63 Maskable Interrupts 4-64 Interrupt Service 4-64 Interrupt Signals 4-66 Interrupt Masking 4-67 Interrupt Processing Example 4-70 Electrical Requirements 4-71 Understanding the Electrical Specifications 4-71 Detailed Electrical Interface Specifications (TMS 9900) 4-75 TMS 9900 Clock Generation 4-75 TMS 9900 Signal Interfacing 4-78 TMS 9940 Microcomputer 4-82 Pin Assignments and Functional Control 4-83 Interrupts 4-83 Decrementer 4-86 CRU Implementation 4-86 Multiprocessor System Interface (MPSI) 4-87 Summary 4-88 9900 FAMILY SYSTEMS DESIGN X-3 TABLE OF CONTENTS Complete Listing of Machine Cycles 4-89 Machine Cycles 4-89 9900 Machine Cycle Sequences 4-90 Terms and Definitions 4-90 Data Derivation Sequences 4-9 1 Workspace Register 4-91 Workspace Register Indirect 4-9 1 Workspace Register Indirect Auto-Increment (Byte Operand) 4-91 Workspace Register Indirect Auto-Increment (Word Operand) 4-9 1 Symbolic 4-92 Indexed 4-92 Instruction Execution Sequences 4-92 A, AB, C, CB, S, SB, SOC, SOCB, SZC, SZCB, MOV, MOVB, COC, CZC, XOR 4-92 MPY (multiply) 4-93 DIV (divide) 4-94 XOP 4-94 CLR, SETQ INV, NEG, INC, INCT, DEC, DECT, SWPB 4-95 ABS 4-95 X 4-96 B 4-96 BL 4-96 BLWP 4-97 LDCR 4-97 STCR 4-98 SBZ, SBO 4-99 TB 4-99 JEQ, JGT, JH, JHE, JL, JLE, JLT, JMP, JNC, JNE, JNQJOCJOP 4-99 SRA, SLA, SRL, SRC 4-100 AI, ANDI, ORI 4-100 CI 4-101 LI 4-101 LWPI 4-101 LIMI 4-101 STWP, STST 4-102 CKON, CKOF, LREX, RSET 4-102 IDLE 4-102 RTWP 4-103 Machine-Cycle Sequences in Response to External Stimuli 4-103 RESET 4-103 LOAD 4-104 Interrupts 4-105 Timing 4-105 T-4 9900 FAMILY SYSTEMS DESIGN TABLE OF CONTENTS Chapter 5.

Pages: 0

Publisher: Science Press (January 1, 2000)

ISBN: 7030113748

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