Download Advanced Engineering Electromagnetics by Constantine A. Balanis PDF
By Constantine A. Balanis
A moment direction in electromagnetics, providing built-in, distinctive assurance of the classical issues, from Maxwell's equations to Green's services. Covers electromagnetic boundary-value difficulties in oblong, cylindrical, and round coordinates. additionally comprises desktop courses for the answer of assigned difficulties.
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Solder bumps or throughhole vias can be utilized for the area array interconnects; however, the processing steps for these two types of interconnects differ considerably. In a manufacturing process developed by IBM and Irvine Sensors, the memory chips are bonded together to form a 3-D silicon cube , . The wafers are processed to interconnect the I/O pads of the die to the bumps on the face of the cube. This metallurgical step is followed by wafer thinning, dicing, and die lamination to create the silicon cube.
2 3-D ICs with Through Silicon (TSV) or Interplane Vias 49 Handle wafer CMOS or SOI (a) Etching TSV CMOS or SOI CMOS or SOI (d) Form through-silicon vias Handle wafer detachment CMOS or SOI (b) Thinned wafer CMOS or SOI (e) Handle wafer (c) Bumps n FIGURE 3-9 Typical fabrication steps for a 3-D IC process: (a) wafer preparation, (b) TSV etching, (c) wafer thinning, bumping, and handle wafer attachment, (d) wafer bonding, and (e) handle wafer removal. Several of the proposed techniques for 3-D ICs support the integration of both CMOS and SOI circuits , .
More advanced recrystallization techniques can provide up to three device layers, where the lowest plane is a CMOS plane while the other two planes are composed of SOI devices . Since there are three device planes in this structure, two isolation layers are required to protect the devices on the lower planes. Measurements from sample structures demonstrate that the threshold voltage of the devices is well controlled with the devices on the upper planes exhibiting low subthreshold currents .