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Download Non-volatile Memories by Pierre-Camille Lacaze, Jean-Claude Lacroix PDF

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By Pierre-Camille Lacaze, Jean-Claude Lacroix

Written for scientists, researchers, and engineers, Non-volatile Memories describes the hot examine and implementations relating to the layout of a brand new iteration of non-volatile digital thoughts. the target is to switch latest thoughts (DRAM, SRAM, EEPROM, Flash, etc.) with a common reminiscence version more likely to succeed in larger performances than the present kinds of reminiscence: super excessive commutation speeds, excessive implantation densities and retention time of data of approximately ten years.

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9). 9. Energy profile of a symmetrical I1/MFG/I2 structure in the presence of a charge on the floating gate MFG. Adapted from [ZHI 12] As a consequence, the greater the charge, the more leakage is significant, and the less time the charge is retained. This is the reason why, in practice, the charge is limited to a number of electrons so that eVs does not exceed a value significantly greater than Wb/2. Under these conditions, the maximum number Nmax of electrons that can be stored in the floating gate is of the order of: Nmax ≈ CmWb/2e2, or Nmax = ε0 εrWb A/a e2 [ZHI 12] 28 Non-volatile Memories Adapted from [YAN 13] and [WON 12] (1) Schottky injection: thermionic injection of electrons into the conduction band (CB) of the insulator (thermal activation of the electrons).

10–100 pJ). It must be recalled that the energy consumption for writing a bit in the case of SRAMs and DRAMs is only 5 × 10-4 and 5 × 10-3 pJ, respectively [YAN 13]. 3. Multilevel cells The previously described floating gate MOSFETs run according to the absence or presence of a charge in FG corresponding to the two values ‘0’ and ‘1’ of a bit. Such a memory is described as a “single level cell” (SLC) memory. Recently, in an attempt to increase integration density, several manufacturers have developed floating gate memories in which, instead of considering only two levels of charge storage (‘0’ and ‘1’) corresponding to two separate values, VTh,0 and VTh,1, several storage levels are defined, which lead to several operating thresholds, and, consequently, memories with several bits, described as “multilevel cells” (MLC) memories.

A cell bit can be read anywhere in the 16,384 blocks of a Flash chip. 5 V is applied to the WLs, except to the one to be read, to which 0 V is applied. The latter behaves like a switch for the current in the BL. If the FG of the cell is “charged” or “discharged” the current in the BL is null (bit ‘0’) or, on the contrary, non-zero (bit ‘1’), respectively. 3. Perspectives for Flash memories Fundamentally, their operation is identical to that of EEPROMs. Compared to the older EEPROMs, however, the storage capacity of Flash memory arrays has been slightly improved by the adoption of new architectures for the control gate and the floating gate, and more recently with the transition to the technology of “charge trap memories” (see Chapter 3).

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